Publications

2023

1. 400G Ethernet Packet Capture Demo Based on Network Development Kit for FPGAs

   Jakub Cabal, Vladislav Válek , Martin Špinler , and 2 more authors

   In IEEE INFOCOM 2023 - IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS) , May 2023

   Abs

   CESNET is ready to present a packet capture demo at 400G networks. As part of its research activities, it has developed a new system for FPGA cards for fast packet reception to DPDK. To simplify the hardware development, we created an open-source Network Development Kit (NDK) framework. Although the demo is presented only on the 400G card, which we have developed in collaboration with Reflex CES, the open-source NDK framework and fast packet capture are available on many other FPGA cards. The open-source framework is ready to use, and we would be happy if you not only use it but also contribute to its further development.

2022

1. FPL Demo: 400G FPGA Packet Capture Based on Network Development Kit

   Jakub Cabal, Jiří Sikora , Štepán Friedl , and 2 more authors

   In 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL) , Aug 2022

   Abs

   CESNET, the Czech NREN (National Research and Education Network), has a long research history in the area of high-speed network monitoring using FPGA accelerated cards. Now, we are ready to present our open-source Network Development Kit for FPGAs11https://github.com/CESNET/ndk-app-minimal/ which is ready for 400 Gbps data transfers via Ethernet and PCI Express. The demo aims to show the possibilities of NDK, which allows users to quickly and easily develop new network applications for FPGA-based acceleration cards. Even high-speed DMA Module fully supported in NDK is available free of charge for academic purposes. It can thus significantly contribute to the spread of 400G technology in the academic community and also among other users. The accelerator card equipped with the Intel Agilex I-Series FPGA will transmit and receive back 400G Ethernet (400GBASE) traffic via external loopback. The received packets will be forwarded via very fast packet DMA transfers directly to the RAM of the host computer.

2021

1. DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers

   Jan Kubálek , Jakub Cabal, Martin Špinler , and 1 more author

   In 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) , May 2021

   Abs

   FPGA accelerator cards are used for packet capture and monitoring in high-speed networks. With the 400G Ethernet technology, there is a need for an ability to transfer data to and from the host memory at the speed of 400Gbps. Currently available architectures (for example [1],[2],[3]) are limited to throughput up to 100Gbps and are therefore not suitable for this use case.This paper presents a vendor-independent DMA architecture that is capable of scaling up to 400Gbps throughput in a single FPGA using two PCIe Gen4 ×16 slots bifurcated into four ×8 interfaces. This architecture is designed to support hundreds of independent DMA channels and supports one or more PCIe endpoints with different configurations. We also demonstrate the performance of the proposed DMA architecture using results measured on an accelerator card with Intel Stratix 10 DX FPGA.

2020

1. Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs

   Lukáš Kekely , Jakub Cabal, Viktor Puš , and 1 more author

   In 2020 23rd Euromicro Conference on Digital System Design (DSD) , Aug 2020

   Abs

   As the throughput of computer networks and other peripheral interfaces is rising, developers are forced to use ever-wider data buses in FPGA designs. However, utilization of wide buses poses a serious threat of performance degradation, especially for the shortest data transactions (packets), as aliasing and alignment overheads on the bus can be extremely increased. In this paper, we propose a novel design method for the description of very wide data buses that we call Multi Buses. The key idea is to enable the processing of multiple transactions per clock cycle with very high and predictable effective throughput even in the worst-case. The feasibility of the proposed method is shown via analysis of achievable performance by both theoretical means and selected proof of concept implementations. Thanks to the proposed method, we were able to design FPGA cores for key operations in networking (e.g. parser, match table, CRC, deparser) with sufficient throughputs for wire-speed packet processing of 400Gbps, lTbps and even 2 Tbps Ethernet links.

2019

1. Scalable P4 Deparser for Speeds Over 100 Gbps

   Jakub Cabal, Pavel Benacek , Jana Foltova , and 1 more author

   In 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) , Apr 2019

   Abs

   The P4 language is a language suitable for the description of packet processing inside a network device. The typical P4 device consists of three main building blocks: Parser, Match+Action Tables and Deparser. The deparsing is the most challenging block because the main task of this block is to assemble the output packet based on changes in Match+Action Tables. This operation can be quite complicated in the case of high-speed networks. In this work, we present the scalable architecture (in term of the throughput) of a deparsing circuit which is suitable for implementation in FPGAs.

2. Effective FPGA Architecture for General CRC

   Lukáš Kekely , Jakub Cabal, and Jan Kořenek

   In Architecture of Computing Systems – ARCS 2019 , Apr 2019

   Abs

   As throughputs of digital networks and memory interfaces are on a constant rise, there is a need for ever-faster implementations of error-detecting codes. Cyclic redundancy checks (CRC) are a common and widely used type of codes to ensure consistency or detect accidental changes of transferred data. We propose a novel FPGA architecture for the computation of the CRC values designed for general high-speed data transfers. Its key feature is allowing a processing of multiple independent data packets (transactions) in each clock cycle, what is a necessity for achieving high overall throughput on very wide data buses. The proposed approach can be effectively used in Ethernet MACs for different speeds, in Hybrid Memory Cube (HMC) controller, and in many other technologies utilizing any kind of CRC. Experimental results confirm that the proposed architecture enables reaching an effective throughput sufficient for utilization in multi-terabit Ethernet networks (over 2 Tbps or over 3000 Mpps) on a single Xilinx UltraScale+ FPGA. Furthermore, a better utilization of FPGA resources is achieved compared to existing CRC implementation for HMC controller (up to 70% savings).

2018

1. High-Speed Computation of CRC Codes for FPGAs

   Jakub Cabal, Lukáš Kekely , and Jan Kořenek

   In 2018 International Conference on Field-Programmable Technology (FPT) , Dec 2018

   Abs

   As the throughput of networks and memory interfaces is on a constant rise, there is a need for ever-faster error-detecting codes. Cyclic redundancy checks (CRC) are a common and widely used to ensure consistency or detect accidental changes of data. We propose a novel FPGA architecture for the computation of the CRC designed for general high-speed data transfers. Its key feature is allowing a processing of multiple independent data packets (transactions) in each clock cycle, what is a necessity for achieving high overall throughput on very wide data buses. Experimental results confirm that the proposed architecture reaches an effective throughput sufficient for utilization in multi-terabit Ethernet networks (over 2 Tbps or over 3000 Mpps) on a single Xilinx UltraScale+ FPGA.

2. Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput

   Jakub Cabal, Pavel Benáček , Lukáš Kekely , and 3 more authors

   In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays , Dec 2018

   Abs

   As throughput of computer networks is on a constant rise, there is a need for ever-faster packet parsing modules at all points of the networking infrastructure. Parsing is a crucial operation which has an influence on the final throughput of a network device. Moreover, this operation must precede any kind of further traffic processing like filtering/classification, deep packet inspection, and so on. This paper presents a parser architecture which is capable to currently scale up to a terabit throughput in a single FPGA, while the overall processing speed is sustained even on the shortest frame lengths and for an arbitrary number of supported protocols. The architecture of our parser can be also automatically generated from a high-level description of a protocol stack in the P4 language which makes the rapid deployment of new protocols considerably easier. The results presented in the paper confirm that our automatically generated parsers are capable of reaching an effective throughput of over 1 Tbps (or more than 2000 Mpps) on the Xilinx UltraScale+ FPGAs and around 800 Gbps (or more than 1200 Mpps) on their previous generation Virtex-7 FPGAs.